1. Field of the Invention
This invention relates to a signal transmission circuit, and more particularly to a signal transmission circuit which is adapted to precharge a signal transmission line and transmit a signal due to whether the charge is maintained or discharged (connected to ground potential).
2. Description of the Prior Art
FIG. 1 is a typical circuit diagram of the conventional signal transmission circuit of a usual precharge system.
In FIG. 1, reference numeral 1 designates a signal transmissin line (bus), which is connected to power supply potential V.sub.cc through a P-channel MOS transistor 2 and to earth potential through a capacitor C.
The signal transmission line 1 connects with a data latch 3 for transmitting a signal and a register 4 for receiving the signal.
The data latch 3 is connected to a gate terminal of an N-channel MOS transistor 5 which connects at one end to earth potential and at the other end to one end of an N-channel MOS transistor 6, the other end of the transistor 6 being connected to the signal transmission line 1, the gate terminal of the same being connected to an output terminal of an AND gate 7.
The AND gate 7 has two inputs, one input of which is given an output clock for outputting the signal to the signal transmission line 1, the other input being given a selecting signal for outputting the signal from the data latch 3 with which the AND gate 7 is connected.
On the other hand, the resister 4 is connected to one end of an N-channel MOS transistor 8 connecting at the other end with the signal transmission line 1. The gate terminal of the N-channel MOS transistor 8 is connected to an input clock for fetching the signal from the signal transmission line 1.
Such conventional signal transmission circuit of precharge system operates as follows:
As shown in FIG. 2(a), precharge clock of negative logic which is given to the gate terminal of the P-channel MOS transistor 2 is at a low level during the precharge period and at a high level during the signal transmission period.
Also, as shown in FIG. 2(b), and an output clock which is at a low level during the precharge period and a high level during the signal transmission period is given to one input of the AND gate 7.
Furthermore, as shown in FIG. 2(c), an input clock which is given to the gate terminal of the N-channel MOS transistor 8 is at a low level during the entire precharge period and during most of the singal transmission period and at a high level only during rear part of the signal transmission period.
At first, during the precharge period, the precharge clock of negative logic is given as the low level signal to the gate terminal at the P-channel MOS transistor, whereby the signal transmission line 1 is connected with power supply potential V.sub.cc. Hence, the capacitor C connected with the signal transmission line 1 is charged as shown in FIG. 2(d).
Next, during the signal transmission period, the output clock of high level signal and selecting signal are given to the AND gate 7, whereby the high level signal is given to the gate terminal of the N-channel MOS transistor 6 and the N-channel MOS transistor 6 conducts. At this time, it will be assumed that the output signal from the data latch 3 is a logical "1" (high level). Since the high level is given also to the gate terminal of the N-channel MOS transistor 5, the N-channel MOS transistor 5 conducts the signal transmission line 1 is grounded through the N-channel MOS transistors 6 and 5. When the signal-transmission line 1 is grounded, as shown by the broken line in FIG. 2(d), the capacitor C is discharged. Thereafter, as shown in FIG. 2(c), when the input clock of high level is given to the gate terminal of the N-channel MOS transistor 8, the low level signal, is inputted to the register 4 through the N-channel MOS transistor 8.
Meanwhile, when the low level signal is outputted from the data latch 3, the N-channel MOS transistor 5 does not conduct. The signal transmission line 1 is not grounded and the capacitor C is not discharged. Accordingly, since the signal transmission line 1 is kept at the high level even at signal transmission period, the high level signal is inputted into the register 4 at the timing of input clock shown in FIG. 2(c).
As is above-mentioned, in the conventional signal transmission circuit of precharge system shown in FIG. 1, the signal of logical "1" (at a high level) or "0" (at a low level) is inverted and inputted to the register 4.
In such conventional signal transmission circuit of precharge system, the longer a physical distance of signal transmission line 1 is, the more unstable the discharge of capacitor C is when the N-channel MOS transistor 5 and 6 conduct. This is shown by the one-dot broken line in FIG. 2(d), thereby creating the phenomenon of difficult discharge.
In light of the above circumstances, a signal trasmission circuit of, for example, the precharge system as shown in FIG. 3 is well-known.
The signal transmission circuit constructed as shown in FIG. 3 divides the signal transmission line (bus) into two line B1 and B2, to prevent the aforesaid precharge potential from being unstable.
In FIG. 3, first and second signal transmission lines (buses) B1 and B2 are connected at one ends to first and second signal input-output terminals 101 and 102 respectively through which the signal is inputted or output. At the other end, a connection is made to one input of a first NOR gate N1 and to one input of a second NOR gate N2 respectively. The signal is transmitted between both the signal input-output terminals 101 and 102 as discussed below.
The other inputs of both the NOR gates N1 and N2 connect with a first precharge signal terminal PC1.
The first signal transmission line B1 connectes with power supply potential V.sub.cc through a first MOS transistor (P-channel type) T51 as a switching element and with earth potential through a second MOS transistor (N-channel type) T52.
The second signal transmission line B2 connects with power supply potential V.sub.cc through a third MOS transistor (P-channel type) T53 at the switching element and with earth potential through a fourth MOS transistor (N-channel type) T54.
The gate terminal of the first and third MOS transistors (both P-channel) T51 and T53 are connected to a precharge signal terminal PC2. Accordingly, when the second precharge signal terminal PC2 is given the low level signal, both the P-channel MOS transistors T51 and T53 conduct so as to feed power supply potential to both signal transmission lines B1 and B2.
On the other hand, the output of the second NOR gate N2 is applied to the gate terminal of the second MOS transistor T52 of N-channel type. The output of the first NOR gate N1 is given to the gate terminal of the fourth MOS transistor T54 of N-channel type. Hence, when the output of the second NOR gate N2 is at a high level, in other words, the first precharge signal terminal PC1 and the second signal input-output terminal 102 are both low level inputs, the second MOS transistor T52 connects the first signal transmission line B1 to earth. Also, when the output of the first NOR gate N1 is at a high level the first precharge signal terminal PC1 and the first signal input-output terminal 101 are both at low level inputs, the fourth MOS transistor T54 connects the second signal transmissin line B2 to earth.
Such signal transmission circuit of precharge system operates as follows:
The first and second precharged signal terminals PC1 and PC2 are given the first and second precharge signals complementary with each other as shown in FIGS. 4(a) and (b). The period of keeping the first precharge signal at a high level is the precharge period, that of keeping the same at a low level being the signal transmission period.
Usually, in the signal transmission cicuit of a precharge system, a signal of logical "1" or "0" is transmitted as a function of whether or not the charge on the signal transmission line (precharge line) during the precharge period is discharged, as described in the explanation of operation in FIG. 1. The operation of the circuit shown in FIG. 3 is as follows:
The low level signal is inputted to the second precharge signal terminal PC2 during the precharge period. The first and third MOS transistors T51 and T53 conduct, and the high level signal is inputted to the first precharge signal terminal PC1. The outputs of both the NOR gates N1 and N2 are at low levels, and the second and fourth MOS transistors T52 and T54, whose gate terminals are given the outputs of NOR gate N1 and N2, do not conduct.
Accordingly, both the signal transmission lines B1 and B2 are connected to the power supply potential V.sub.cc during the precharge period. This allows them to be precharged from the power supply potential.
Next, since the second precharge signal terminal PC2 is turned to a high level during the signal transmission period, the first and third MOS transistors T51 and T53 do not conduct. Since the input signal to the first precharge terminal PC1 turns to low level, the outputs of both the NOR gates N1 and N2 change corresponding to the level of the input signal to the first signal input-output terminal 101 and second signal input-output terminal 102.
Now, assuming that, for example, the input signal to the first signal input-output terminal 101 (the signal to be transmitted from the first signal input-output terminal 101 to the second signal input-output terminal 102), is a logical "0", the input signal to the first signal input-output terminal 101 is a low level. Hence, the output of the first NOR gate N1 turns to a high level and is given to the gate terminal of the fourth MOS transistor T54. Accordingly, since the fourth MOS transistor T54 conducts, the second signal transmission line B2 is grounded through the fourth MOS transistor T54 and the signal output of the second signal input-output terminal 102 is at a low level.
On the contrary, when the signal to be transmitted is a logical "1", since the first signal input-output terminal 101 is given the high level signal, the output of the first NOR gate N1 is at a low level and the fourth MOS transistor T54, whose gate terminal is given the low level output, maintains the not-conductive state. Therefore, the signal output from the second signal output terminal 102 has a high level.
Namely, in the signal transmission cicuit shown in FIG. 3, the signal of logical "1" or "0" inputted from the first signal input-output terminal 101 (or the second signal input-output terminal 102) is inverted to be outputted to the second signal input-output terminal 102 (or the first signal input-output terminal 101).
Incidentally, in the aforesaid construction shown in FIG. 3 the two input NOR gates are used, but the usual two-input NOR gate adopts construction as shown in FIG. 5. The two references IN designate input terminals, the one reference OUT an output terminal, four MOS transistors TR1 through TR4.
The conventional signal tranmsmission circuit of a precharge system, which is constructed as above-mentioned, requires a total of 12 MOS transistors to be used as the switching element, thereby creating problems in that the number of elements must be increased.